Conventionally, a hierarchical memory configuration composed of a cache memory, a main memory, and a file system has been adopted as a memory area in which data used by a core when executing a process is stored. Because the hierarchical memory configuration improves data access speed, the system can be expected to operate faster. In the hierarchical memory configuration, a cache memory, which operates faster than other memories, has a limited memory capacity. For this reason, data stored in the cache memory is replaced using a least recently used (LRU) algorithm, etc. (see, e.g., Japanese Laid-Open Patent Application No. H6-175923).
A multi-core processor system having multiple cores is in wide use in recent years. The multi-core processor system causes the cores to execute tasks in parallel and thereby, significantly improves processing performance (see, e.g., Japanese Laid-Open Patent Application No. H6-175923). In parallel execution of tasks by the multi-core processor system, however, when data on the cache memory of each core is rewritten, a process of synchronizing the written data with data on the cache memory of another core is required.
One method of data synchronization is, for example, a snoop cache mechanism that is a mechanism for establishing cache coherence between cores. The snoop cache mechanism is actuated when data is rewritten that is on the cache memory of a given core and is share by another core. Rewriting data on the cache memory is detected by a snoop controller incorporated in the cache memory of another core. Through a bus between cache memories, the snoop controller reflects a new value resulting from the data rewriting in the cache memory of the other core (see, e.g., Japanese Laid-Open Patent Application No. H10-240698).
An embedded system requires parallel execution of multiple applications. Hence, techniques for realizing parallel execution have been provided. Such techniques are disclosed as, for example, multi-task processing of switching a task executed at one core by time sharing, etc., a distributed process of causing multiple cores to execute multiple tasks, and a process given by combining these processes together (see, e.g., Japanese Laid-Open Patent Application No. H11-212869).
In the case of the multi-core processor system, however, the execution of parallel tasks by multiple cores requires synchronization between cache memories and the execution of multi-task processing results in frequent rewriting of a cache memory. Such cache memory synchronization and rewriting often cause the performance of the system to drop.
FIG. 20 is an explanatory diagram of an example of an operation of a snoop in multi-core parallel processing. In a multi-core processor system 2000, multiple cores (e.g., CPU #0 and CPU #1 in FIG. 20) execute parallel processing in which the CPUs execute processes simultaneously. In the execution of parallel processing, when the CPUs simultaneously execute tasks using common data, if the data on one cache memory (e.g., either a cache L1$0 or a cache L1$1) is rewritten, a snoop 120 performs a synchronization process. For example, when the CPU #0 rewrites a value for variable a in data stored in the cache L1$0, the snoop 120 rewrites a value for variable a in the cache L1$1 via a bus.
If data rewriting by the snoop 120 occurs frequently, the bus connecting the cache L1$0 to the cache L1$1 becomes congested, which leads to a drop in system performance. In addition, frequent data rewriting increases bus transactions, causing the bus of the snoop 120 to be occupied. Under such conditions, when a request for executing a different process with a real-time constraint is issued, the condition hampers access by the process with the real-time constraint to the cache memory of the process, which could develop into a serious performance-related problem.
FIG. 21 is an explanatory diagram of an example of cache rewriting in multi-task processing. When the multi-core processor system 2000 executes multi-task processing, the multi-core processor system 2000 performs task switching of switching a task to be executed, depending on a condition of executing of tasks. For example, in FIG. 21, the multi-core processor system 2000 executes multi-task processing on tasks #0 to #2.
It is assumed that task switching occurs in a state where the CPU #0 executes the task #0 and the CPU #1 executes the task #2, as depicted on the left in FIG. 21. As a result of the task switching, the task to be executed by the CPU #0 is changed from the task #0 to the task #1, as depicted on the right in FIG. 21. When the task to be executed is switched, data that is stored in the cache L1$0 and used by the task #0, is rewritten into data used by the task #1.
After the data stored in the cache L1$0 is rewritten, if a process that has been executed before the data rewriting is resumed, the CPU #0 must again read from memory 140, the data to be used. Even when data stored in the cache memory of a task-executing CPU is rewritten as a result of task switching, the rewritten data is not used by the CPU in many cases. The rewriting of data that is not subsequently used poses a problem in that the data rewriting causes a drop in the performance of the CPU using the cache memory.